Ashwini Vaishnaw interacts with Semiconductor Chip Design Companies

Union Minister for Electronics and Information Technology Ashwini Vaishnaw, interacted with semiconductor chip design companies approved under the Design Linked Incentive (DLI) Scheme of the Semicon India Programme in New Delhi today. The interaction focused on reviewing progress, understanding design innovations, and reinforcing the Government’s commitment to building a robust, indigenous semiconductor design ecosystem. The DLI Scheme aims to accelerate domestic chip design capabilities by supporting startups and companies across areas such as SoCs, telecom, power management, AI, and IoT, thereby strengthening India’s self-reliance in critical semiconductor technologies.
Highlighting the success of the Design Linked Incentive (DLI) Scheme, the Minister noted that while expectations were modest initially, the programme today supports 24 startups, many of which have already completed tape-outs, validated products and found market traction. This, he said, has validated the government’s core approach of removing key barriers faced by semiconductor startups by providing access to advanced design tools, IP libraries, wafer and tape-out support—an architecture of support that is unique globally.
Referring to infrastructure development, the Minister stated that SCL Mohali will support tape-outs in the 180-nanometre range, while advanced nodes up to 28 nanometres will be enabled through the upcoming fabrication facility at Dholera, providing a strong manufacturing base to complement domestic design capabilities. He also highlighted the government’s sustained focus on talent development, noting that against a target of 85,000 skilled professionals over ten years, over 67,000 semiconductor professionals have already been trained in just four years.(updated on 27thjanuary 2026)